1. Field of the Invention
The invention relates to phase-locked loop (PLL) circuits. More particularly, the invention relates to a PLL whose loop bandwidth replicates or tracks its input frequency.
2. Description of the Related Art
A phase-locked loop (PLL) is a circuit that generates a periodic output signal, or clock, that has a constant phase relationship with a periodic input signal. PLLs are closed loop frequency control systems whose operation depends on the detection of the phase difference between the input and output signals of the circuit, and which are used in many types of measurement, microprocessor and communication applications. Often, PLLs are used to generate clocks, or to recover clocks from received data in such applications.
Typically, a conventional PLL used for clock generation includes a phase/frequency detector (PFD), a charge pump, a loop filter, a voltage-controlled oscillator (VCO) or current-controlled oscillator (ICO), which generates the PLL output clock, and a frequency divider.
The PFD measures the difference in phase between an input clock and a feedback clock, which may be the PLL output clock itself, or a clock generated by passing the PLL output clock through a frequency divider. The PFD generates an error signal that is proportional to this measured phase difference, and the charge pump generates a current that is proportional to this error signal. The charge pump current is input to the loop filter, and the loop filter outputs a voltage that is input to the VCO. The frequency of the PLL output clock generated by the VCO is controlled by the loop filter voltage.
Under proper conditions, the loop characteristics will be such that the phase and frequency of the feedback clock derived from the PLL output clock will exactly equal the frequency and phase of the PLL input clock. In this condition, the PLL is said to be “locked”. Once the PLL is locked, if the phase of the input clock varies in time, then the phase of the output clock will track it, thus keeping the phase of the feedback clock equal to the phase of the input clock.
The ability of a PLL to track variations in the phase of its input clock is quantified by a measure known as the PLL jitter transfer function. The jitter transfer function of a PLL is essentially lowpass in nature; the output phase of the PLL will fully track low frequency variations in the input phase, but will only partially track, or not track at all, high frequency variations in input phase. An important quantity associated with the jitter transfer function is the closed loop bandwidth of the PLL. The closed loop bandwidth of a PLL is the frequency of phase modulation at which the magnitude of the jitter transfer function drops by 3 dB from its low frequency limit.
In addition to providing an indication of the upper limit of the input phase modulation frequency which can be fully tracked by the PLL, it is also known that the closed loop bandwidth quantifies the ability of the PLL to attenuate random noise originating within the VCO. Specifically, VCO phase noise is attenuated at frequencies below the PLL loop bandwidth, and passed at frequencies above the loop bandwidth. Since VCO phase noise is a significant source of jitter in most PLLs used in clock generator applications, maximizing the loop bandwidth is a desirable characteristic for most PLLs.
However, in order for the PLL loop to be stable, the loop bandwidth of the PLL is limited to a small fraction of the frequency of the PLL input clock. Specifically, it is widely agreed upon that the loop bandwidth should not significantly exceed 10% of the PLL input clock frequency. Thus, in order to maintain an adequate loop stability margin, while still attenuating VCO phase noise as much as possible, making the loop bandwidth a substantially constant fraction of the PLL input frequency (e.g. 10%) over a specified range of input frequencies is a desirable design goal for most PLLs used in clock synthesizer applications.
In addition to random noise within the VCO, noise on the loop filter voltage, which controls the frequency of the VCO, is also a significant source of jitter in many PLLs. To reduce this noise, it is desirable that the VCO gain, KVCO, which is defined as the ratio of the change in PLL output frequency to a small change in loop filter voltage, be minimized. However, in many clock synthesizer applications, it is also desirable that a single PLL be capable of operating over a wide range of output frequencies. In a standard charge-pump PLL, the required operating range places a lower limit on the VCO gain. Specifically KVCO must meet the following requirement
      K    VCO    >            Δ      ⁢                          ⁢              F        VCO                    Δ      ⁢                          ⁢              V        LF            where ΔFVCO is the difference between the required maximum and minimum operating frequencies for the PLL output clock, and ΔVLF is the peak-to-peak range of the loop filter voltage. In many applications, this minimum KVCO may be a much higher gain than is compatible with the requirement for low jitter. Thus, for applications which require a low-jitter PLL that also covers a wide operating range, it is desirable to choose an architecture in which the VCO gain is independent of the operating frequency range.
U.S. Pat. No. 5,942,949 discloses a PLL with an oscillator architecture that includes autotrim. Autotrim is a feature or procedure that calibrates the center frequency of the VCO, which is defined as the operating frequency of the oscillator when the loop filter voltage is equal to a suitable reference voltage, during a power-up or reset state of the PLL. This autotrim feature allows the PLL to operate across a relatively wide output frequency range while still maintaining a relatively low VCO gain. However, in the PLL architecture disclosed in U.S. Pat. No. 5,942,949, the loop bandwidth does not replicate or track the input frequency, i.e., the update rate of the PFD, and thus the VCO phase noise is not optimally attenuated when the PLL is used over a wide range of input frequencies.
The article “Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques,” IEEE Journal of Solid-State Circuits, Vol. 31, No. 11, November 1996, describes self-biasing PLL designs in which the loop bandwidth tracks the PLL input frequency. However, in these PLLS, the VCO gain must be large enough to allow the PLL to operate across a relatively wide range of operating frequencies and to compensate for process and temperature variations. Such a large VCO gain disadvantageously increases the sensitivity of the output jitter of the PLL to various noise sources, including noise in the loop filter voltage.
Accordingly, it would be desirable to have available a PLL with a relatively wide input and output operating frequency range, a relatively low VCO gain that is substantially independent of the operating output frequency range, and a loop bandwidth that tracks its input frequency.